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STA505
40V 3.5A QUAD POWER HALF BRIDGE
1

FEATURES
MULTIPOWER BCD TECHNOLOGY MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION 200m RdsON COMPLEMENTARY DMOS OUTPUT STAGE CMOS COMPATIBLE LOGIC INPUTS THERMAL PROTECTION THERMAL WARNING OUTPUT UNDER VOLTAGE PROTECTION
Figure 1. Package
PowerSO36
Table 1. Order Codes
Part Number STA505 STA50513TR Package PowerSO36 in Tape & Reel

current capability.
2
DESCRIPTION
STA505 is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (Binary mode) with half
The device is particularly designed to make the output stage of a stereo All-Digital High Efficiency (DDXTM) amplifier capable to deliver 50 + 50W @ THD = 10% at Vcc 30V output power on 8 load and 80W @ THD = 10% at Vcc 36V on 8 load in single BTL configuration. The input pins have threshold proportional to VL pin voltage.
Figure 2. Audio Application Circuit (Dual BTL)Pin Description
VCC1A IN1A IN1A +3.3V VL CONFIG PWRDN R57 10K R59 10K C58 100nF TH_WAR IN1B VDD VDD VSS VSS C58 100nF C53 100nF C60 100nF IN2A VCCSIGN VCCSIGN IN2A GND-Reg GND-Clean 21 22 33 34 M17 35 8 9 36 31 20 19 M16 M15 REGULATORS 7 VCC2A C32 1F OUT2A OUT2A 6 GND2A PWRDN FAULT 23 24 25 27 26 TRI-STATE PROTECTIONS & LOGIC M5 28 30 M4 13 M2 29 M3 15 17 16 C30 1F OUT1A OUT1A 14 GND1A C52 330pF +VCC C55 1000F
L18 22H C20 100nF R98 6 C99 100nF C23 470nF C101 100nF
8
12
VCC1B C31 1F OUT1B OUT1B GND1B R63 20 R100 6 C21 100nF L19 22H
11 10
TH_WAR IN1B
L113 22H C110 100nF C109 330pF R103 6 R104 20
4
VCC2B C33 1F OUT2B OUT2B
R102 6 C111 100nF
3 2
C107 100nF C108 470nF C106 100nF
8
IN2B
IN2B GNDSUB
32 M14
L112 22H
1
5
GND2B
D00AU1148B
February 2006
Rev. 11 1/10
STA505
Table 2. Pin Function
N 1 2;3 4 5 6 7 8;9 10 ; 11 12 13 14 15 16 ; 17 18 19 20 21 ; 22 23 24 29 25 26 27 28 29 30 31 32 33 ; 34 35 ; 36 Pin GND-SUB OUT2B Vcc2B GND2B GND2A Vcc2A OUT2A OUT1B Vcc1B GND1B GND1A Vcc1A OUT1A NC GND-clean GND-Reg Vdd VL CONFIG IN1A PWRDN TRI-STATE FAULT TH-WAR IN1A IN1B IN2A IN2B Vss Vcc Sign Substrate ground Output half bridge 2B Positive Supply Negative Supply Negative Supply Positive Supply Output half bridge 2A Output half bridge 1B Positive Supply Negative Supply Negative Supply Positive Supply Output half bridge 1A Not connected Logical ground Ground for regulator Vdd 5V Regulator referred to ground High logical state setting voltage Configuration pin Input of half bridge 1A Stand-by pin Hi-Z pin Fault pin advisor Thermal warning advisor Input of half bridge 1A Input of half bridge 1B Input of half bridge 2A Input of half bridge 2B 5V Regulator referred to +Vcc Signal Positive Supply Description
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Table 3. Functional Pin Status
PIN NAME FAULT FAULT (*) TRI-STATE TRI-STATE PWRDN PWRDN THWAR THWAR(*) CONFIG CONFIG(**) Logical value 0 1 0 1 0 1 0 1 0 1 IC -STATUS Fault detected (Short circuit, or Thermal ..) Normal Operation All powers in Hi-Z state Normal operation Low absorpion Normal operation Temperature of the IC =130C Normal operation Normal Operation OUT1A=OUT1B ; OUT2A=OUT2B (IF IN1A = IN1B; IN2A = IN2B)
(*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. (**): To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)
Figure 3. Pin Connection
VCCSign VCCSign VSS VSS IN2B IN2A IN1B IN1A TH_WAR FAULT TRI-STATE PWRDN CONFIG VL VDD VDD GND-Reg GND-Clean
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
D01AU1273
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
GND-SUB OUT2B OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT2A OUT1B OUT1B VCC1B GND1B GND1A VCC1A OUT1A OUT1A N.C.
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Table 4. Absolute Maximum Ratings
Symbol VCC Vmax Top Tstg, Tj Parameter DC Supply Voltage (Pin 4,7,12,15) Maximum Voltage on pins 23 to 32 Operating Temperature Range Storage and Junction Temperature Value 40 5.5 -40 to 90 -40 to 150 Unit V V C C
Table 5. Thermal Data
Symbol Tj-case TjSD Twarn thSD Parameter Thermal Resistance Junction to Case (thermal pad) Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis 150 130 25 Min. Typ. Max. 2.5 Unit C/W C C C
Table 6. Electrical Characteristcs (VL = 3.3V; Vcc = 30V; Tamb = 25C; fsw = 384Khz; unless otherwise specified)
Symbol RdsON Idss gN gP Dt_s Dt_d td ON td OFF tr tf VCC VIN-High VIN-Low IIN-H IIN-L Parameter Power Pchannel/Nchannel MOSFET RdsON Power Pchannel/Nchannel leakage Idss Id=1A; Vcc=35V 95 95 10 20 50 100 100 25 25 10 36 VL/2 +300mV VL/2 300mV Pin voltage = VL Pin voltage = 0.3V 1 1 Test conditions Min. Typ. 200 Max. 270 50 Unit m A % % ns ns ns ns ns ns V V V A A
Power Pchannel RdsON Matching Id=1A Power Nchannel RdsON Matching Low current Dead Time (static) Id=1A see test circuit no.1; see fig. 1
High current Dead Time (dinamic) L=22H; C = 470nF; Rl = 8 Id=3.5A; see fig. 3 Turn-on delay time Turn-off delay time Rise time Fall time Supply voltage operating voltage High level input voltage Low level input voltage High level Input current Low level input current Resistive load Resistive load Resistive load; as fig.1; Resistive load; as fig. 1;
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Symbol Parameter Test conditions Min. Typ. 35 0.8 1.7 3 Max. Unit A V V mA
IPWRDN-H High level PWRDN pin input current VLow VHigh IVCCPWRDN IFAULT Low logical state voltage VLow VL = 3.3V (pin PWRDN, TRISTATE) (note 1) High logical state voltage VHigh VL = 3.3V (pin PWRDN, TRISTATE) (note 1) Supply current from Vcc in Power Down Output Current pins FAULT -TH-WARN when FAULT CONDITIONS Supply current from Vcc in Tristate Supply current from Vcc in operation both channel switching) Isc (short circuit current limit) (note 2) Undervoltage protection threshold Output minimum pulse width No Load 70 PWRDN = 0
Vpin = 3.3V Tri-state=0 Input pulse width = 50% Duty; Switching Frequency = 384KHz; No LC filters; 3.5
1 22 50
mA mA mA
IVCC-hiz IVCC
IVCC-q VUV tpw-min
6 7
8
A V
150
ns
Table 7.
Notes: 1. The following table explains the VLow, VHigh variation with VL
VL 2.7 3.3 5
VLow min 0.7 0.8 0.85
VHigh max 1.5 1.7 1.85
Unit V V V
Note 2: See relevant Application Note AN1994
Table 8. Logic Truth Table (see fig. 5)
TRI-STATE 0 1 1 1 1 INxA x 0 0 1 1 INxB x 0 1 0 1 Q1 OFF OFF OFF ON ON Q2 OFF OFF ON OFF ON Q3 OFF ON ON OFF OFF Q4 OFF ON OFF ON OFF OUTPUT MODE Hi-Z DUMP NEGATIVE POSITIVE Not used
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Figure 4. Test Circuit.
OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50%
M58
DTr OUTxY
M57
DTf
INxY
R 8
+ -
V67 = vdc = Vcc/2
D03AU1458
gnd
Figure 5.
+VCC
Q1 INxA OUTxA
Q2 OUTxB INxB
Q3
Q4
GND
D00AU1134
Figure 6.
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B
DTout(A) M58 Q1 OUTxA Rload=8 L67 22 C69 470nF DTout(B) L68 22 C70 470nF Q2 OUTxB M64
DTin(A) INxA
DTin(B) INxB
Iout=4.5A M57 Q3
Iout=4.5A Q4 M63
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure
D00AU1162A
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Figure 7. Typical Single BTL Configuration to Obtain 80W @ THD 10%, RL = 8, VCC = 36V (note 1)
+3.3V 100nF VL 23 18 17 16 11 10 N.C. 22H GND-Clean GND-Reg 10K 100nF X7R VDD VDD CONFIG TH_WAR nPWRDN 10K TH_WAR PWRDN FAULT TRI-STATE 100nF IN1A IN1B IN2A IN2B VSS VSS 100nF X7R 100nF X7R Add. VCCSIGN VCCSIGN GNDSUB 19 20 OUT1A OUT1A OUT1B OUT1B OUT2A 9 8 OUT2B 3 2 VCC1A 1F X7R OUT2B 22H +36V 2200F 63V OUT2A 330pF 22 1/2W 6.2 1/2W 6.2 1/2W 100nF FILM 100nF X7R 470nF FILM 100nF X7R 100nF FILM
21 22 24 28 25 27 26
8
15
29 30 31 32 33 34
12
VCC1B VCC2A
IN1A
7
+36V 1F X7R
IN1B
4 14
VCC2B GND1A GND1B
35
13 GND2A
36 1
6 GND2B 5
D01AU1274
Note: 1. "A PWM modulator as driver is needed . In particular, this result is performed using the STA30X+STA50X demo board".
Figure 8. Typical Quad Half Bridge Configuration
VCC1P IN1A IN1A +3.3V VL CONFIG PWRDN R57 10K R59 10K C58 100nF TH_WAR IN1B VDD VDD VSS VSS C58 100nF C53 100nF C60 100nF IN2A VCCSIGN VCCSIGN IN2A GND-Reg GND-Clean 21 22 33 34 M17 35 8 9 36 31 20 19 M16 M15 OUTPR OUTPR 6 PGND2P R43 20 C43 330pF L13 22H C73 100nF R53 6 C83 100nF R66 5K REGULATORS 7 VCC2P PWRDN FAULT 23 24 25 27 26 TRI-STATE PROTECTIONS & LOGIC M5 28 30 M4 13 M2 29 M3 15 17 16 OUTPL OUTPL 14 PGND1P R41 20 C41 330pF L11 22H C71 100nF R51 6 C81 100nF R62 5K R61 5K +VCC C21 2200F
C31 820F
C91 1F
4
12
VCC1N C51 1F OUTNL OUTNL PGND1N C61 100nF L12 22H R42 20 C42 330pF C72 100nF R52 6 C82 100nF R64 5K
11 10
TH_WAR IN1B
R63 5K
C32 820F
C92 1F
4
R65 5K
C33 820F
C93 1F
4
4
VCC2N C52 1F OUTNR OUTNR C62 100nF L14 22H R44 20 C44 330pF C74 100nF R54 6 C84 100nF R68 5K
3 2
IN2B
R67 5K
C34 820F
IN2B GNDSUB
32 M14
1
5
PGND2N
C94 1F
4
D03AU1474
For more information refer to the application notes AN1456 and AN1661
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Figure 9. Power SO36 (Slug up) Mechanical Data & Package Dimensions
DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s mm TYP. inch TYP.
MIN. 3.25 3.1 0.8 0.030 0.22 0.23 15.8 9.4
MAX. 3.43 3.2 1 -0.040 0.38 0.32 16 9.8
MIN. 0.128 0.122 0.031 0.0011 0.008 0.009 0.622 0.37
MAX. 0.135 0.126 0.039 -0.0015 0.015 0.012 0.630 0.38
OUTLINE AND MECHANICAL DATA
0.2
0.008
1 13.9 10.9 5.8 2.9 0.65 11.05 0 15.5 0.8 0.075 15.9 1.1 1.1 10 8 0 0.61 0.031 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.228 0.114
0.039 0.57 0.437 0.114 0.244 1.259 0.026 0.435 0.003 0.625 0.043 0.043 10 8
PowerSO36 (SLUG UP)
(1) "D and E1" do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006") (2) No intrusion allowed inwards the leads.
7183931 D
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Table 9. Revision History
Date December 2003 June 2004 November 2004 February 2006 Revision 8 9 10 11 Description of Changes First Issue in EDOCS DMS Note 2: See relevant Application Note AN1994 Changed Vcc in Electrical Characteristics from 9 min to 10 min Changed Top value on Table 4.
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